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authorNoah Abradjian <noah.abradjian@amd.com>2019-11-22 11:47:52 -0500
committerAlex Deucher <alexander.deucher@amd.com>2019-12-18 16:09:08 -0500
commit0120e8b8451c6a0fdc564ba9b30d75fd6995bbc4 (patch)
tree3d223eeb7c4a87ac2c0a205ceca712b6b825101f /drivers/gpu/drm/amd/display/dc/dcn20
parentded6119e825aaf0bfc7f2a578b549d610da852a7 (diff)
drm/amd/display: Use pipe_count for num of opps
[Why] There is one opp per pipe. For certain RN parts, the fourth pipe is disabled, so there is no opp for it. res_cap->num_opp is hardcoded to 4, so if we use that to iterate over opps we will crash. [How] Use the pipe_count value instead, which is not hardcoded and so will have the correct number. Signed-off-by: Noah Abradjian <noah.abradjian@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 32878a65bdd7..cafbd08f1cf2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1357,7 +1357,7 @@ static void dcn20_update_dchubp_dpp(
// MPCC inst is equal to pipe index in practice
int mpcc_inst = pipe_ctx->pipe_idx;
int opp_inst;
- int opp_count = dc->res_pool->res_cap->num_opp;
+ int opp_count = dc->res_pool->pipe_count;
for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {