diff options
| author | Sung Joon Kim <sungkim@amd.com> | 2023-10-11 15:48:51 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-11-03 12:18:33 -0400 |
| commit | 995dedb7a4fa9703d1ae584914b0aa12b5da454c (patch) | |
| tree | 68f0407a1aa5189d3cee11726fcb69db1b25975f /drivers/gpu/drm/amd/display/dc/dcn30 | |
| parent | 23618280cca543183d29ae4f286e3319066774d2 (diff) | |
drm/amd/display: Program plane color setting correctly
[why]
There are some registers for plane
color that are skipped programming
on resume. Need to add those as part
of the sequence.
[how]
Add new function hook for programming
plane color control.
Reviewed-by: Duncan Ma <duncan.ma@amd.com>
Acked-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn30')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h | 5 |
2 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c index 2861d974fcf6..75547ce86c09 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c @@ -316,7 +316,7 @@ bool hubp3_program_surface_flip_and_addr( return true; } -static void hubp3_program_tiling( +void hubp3_program_tiling( struct dcn20_hubp *hubp2, const union dc_tiling_info *info, const enum surface_pixel_format pixel_format) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h index 8a32772d4e91..b010531a7fe8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h @@ -278,6 +278,11 @@ void hubp3_setup( struct _vcs_dpi_display_rq_regs_st *rq_regs, struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); +void hubp3_program_tiling( + struct dcn20_hubp *hubp2, + const union dc_tiling_info *info, + const enum surface_pixel_format pixel_format); + void hubp3_dcc_control(struct hubp *hubp, bool enable, enum hubp_ind_block_size blk_size); |