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authorYongqiang Sun <yongqiang.sun@amd.com>2017-11-24 16:31:03 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-12-14 11:00:35 -0500
commit904623ee5936e2226009b2f238f28781aecd2565 (patch)
treebba0b5b3e1634df87d77ba0949fc75742dd08bf9 /drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
parent73da927b083737a8923c1bbc850274adffca1257 (diff)
drm/amd/display: Move wait for hpd ready out from edp power control.
It may take over 200ms for wait hpd ready. To optimize the resume time, we can power on eDP in init_hw, wait for hpd ready when doing link training. also create separate eDP enable function to make sure eDP is powered up before doing and DPCD access, as HPD low will result in DPDC transaction failure. After optimization, setpowerstate 145ms -> 9.8ms, DPMS 387ms -> 18.9ms Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 03431134c088..b6215ba514d8 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -199,6 +199,7 @@ struct hw_sequencer_funcs {
void (*edp_backlight_control)(
struct dc_link *link,
bool enable);
+ void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
};