diff options
| author | Tony Cheng <tony.cheng@amd.com> | 2017-02-28 21:30:32 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 17:17:51 -0400 |
| commit | d98e5cc2ddacb34e9cdf1c06dce2758198af0120 (patch) | |
| tree | 66a0ce231d31e37b4e2e1eaa2aede4f95a876bed /drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | |
| parent | 2d60ded1325e0b4407aaa5396d1b331ea58f4f85 (diff) | |
drm/amd/display: clean up and simply locking logic
always take update lock instead of using HW built in update
lock trigger with write to primary_addr_lo.
we will be a little more inefficient with the extra registers
write to lock, but this simplify code and make it always correct.
Will revisit locking optimization once update sequence mature
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index a902de52107f..612910e720af 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -39,7 +39,6 @@ enum pipe_lock_control { PIPE_LOCK_CONTROL_BLENDER = 1 << 1, PIPE_LOCK_CONTROL_SCL = 1 << 2, PIPE_LOCK_CONTROL_MODE = 1 << 3, - PIPE_LOCK_CONTROL_MPCC_ADDR = 1 << 4 }; struct dce_hwseq_wa { |