drm/amd/pm: Enable performance determinism on aldebaran

Performance Determinism is a new mode in Aldebaran where PMFW tries to
maintain sustained performance level. It can be enabled on a per-die
basis on aldebaran. To guarantee that it remains within the power cap,
a max GFX frequency needs to be specified in this mode. A new
power_dpm_force_performance_level, "perf_determinism", is defined to enable
this mode in amdgpu. The max frequency (in MHz) can be specified through
pp_dpm_sclk. The mode will be disabled once any other performance level
is chosen.

Ex: To enable perf determinism at 900Mhz max gfx clock

echo perf_determinism > /sys/bus/pci/devices/.../power_dpm_force_performance_level
echo max 900 > /sys/bus/pci/devices/.../pp_dpm_sclk

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 88 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index f2a64bd47f42..3cc4e6f556c3 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -292,6 +292,7 @@ static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
 			(level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 			(level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 			(level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
+			(level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" :
 			"unknown");
 }
 
@@ -328,6 +329,8 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
 		level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 	} else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 		level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
+	} else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) {
+		level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM;
 	}  else {
 		return -EINVAL;
 	}
@@ -1039,6 +1042,83 @@ static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
  */
 #define AMDGPU_MASK_BUF_MAX	(32 * 13)
 
+static int amdgpu_read_clk(const char *buf,
+		size_t count,
+		uint32_t *min,
+		uint32_t *max)
+{
+	int ret;
+	char *tmp;
+	char *token = NULL;
+	char *tag;
+	char *value;
+	char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
+	const char delimiter[3] = {' ', '\n', '\0'};
+	size_t bytes;
+	int i = 0;
+
+	bytes = min(count, sizeof(buf_cpy) - 1);
+	memcpy(buf_cpy, buf, bytes);
+	buf_cpy[bytes] = '\0';
+	tmp = buf_cpy;
+
+	*min = *max = 0;
+	while (i < 2) {
+		ret = -EINVAL;
+		token = strsep(&tmp, delimiter);
+		if (!token || !*token)
+			break;
+		tag = token;
+
+		token = strsep(&tmp, delimiter);
+		if (!token || !*token)
+			break;
+		value = token;
+
+		if (!strncmp(tag, "min", strlen("min")))
+			ret = kstrtou32(value, 0, min);
+		else if (!strncmp(tag, "max", strlen("max")))
+			ret = kstrtou32(value, 0, max);
+
+		if (ret)
+			break;
+		++i;
+	}
+
+	/* should get a non-zero value for min or max */
+	if (!*min && !*max)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int amdgpu_set_clk_minmax(struct amdgpu_device *adev,
+		uint32_t clk_type,
+		uint32_t min,
+		uint32_t max)
+{
+	int ret;
+
+	if (!is_support_sw_smu(adev) || amdgpu_sriov_vf(adev))
+		return -EINVAL;
+
+	ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
+	if (ret < 0) {
+		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+		return ret;
+	}
+
+	ret = smu_set_soft_freq_range(&adev->smu, clk_type, min, max);
+
+	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
+	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+
+	if (ret)
+		return -EINVAL;
+
+	return 0;
+}
+
 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
 {
 	int ret;
@@ -1077,10 +1157,18 @@ static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev,
 	struct amdgpu_device *adev = drm_to_adev(ddev);
 	int ret;
 	uint32_t mask = 0;
+	uint32_t min;
+	uint32_t max;
 
 	if (amdgpu_in_reset(adev))
 		return -EPERM;
 
+	ret = amdgpu_read_clk(buf, count, &min, &max);
+	if (!ret) {
+		ret = amdgpu_set_clk_minmax(adev, SMU_GFXCLK, min, max);
+		return ret ? ret:count;
+	}
+
 	ret = amdgpu_read_mask(buf, count, &mask);
 	if (ret)
 		return ret;