diff options
| author | Ma Jun <Jun.Ma2@amd.com> | 2023-10-12 09:33:45 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-10-20 15:11:26 -0400 |
| commit | 1958946858a62b6b5392ed075aa219d199bcae39 (patch) | |
| tree | 061a7c965efd985893d23a06ce59ed674a73f197 /drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | |
| parent | afcf949cf331de791e3fbfc65c0bb82dd9df6d57 (diff) | |
drm/amd/pm: Support for getting power1_cap_min value
Support for getting power1_cap_min value on smu13 and smu11.
For other Asics, we still use 0 as the default value.
Signed-off-by: Ma Jun <Jun.Ma2@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c')
| -rw-r--r-- | drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 34 |
1 files changed, 20 insertions, 14 deletions
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index 1e710c0c9042..090249b6422a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -620,11 +620,12 @@ static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *s static int sienna_cichlid_get_power_limit(struct smu_context *smu, uint32_t *current_power_limit, uint32_t *default_power_limit, - uint32_t *max_power_limit) + uint32_t *max_power_limit, + uint32_t *min_power_limit) { struct smu_11_0_7_powerplay_table *powerplay_table = (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table; - uint32_t power_limit, od_percent; + uint32_t power_limit, od_percent_upper, od_percent_lower; uint16_t *table_member; GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member); @@ -639,21 +640,26 @@ static int sienna_cichlid_get_power_limit(struct smu_context *smu, if (default_power_limit) *default_power_limit = power_limit; - if (max_power_limit) { - if (smu->od_enabled) { - od_percent = - le32_to_cpu(powerplay_table->overdrive_table.max[ - SMU_11_0_7_ODSETTING_POWERPERCENTAGE]); + if (smu->od_enabled) { + od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]); + od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]); + } else { + od_percent_upper = 0; + od_percent_lower = 100; + } - dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", - od_percent, power_limit); + dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n", + od_percent_upper, od_percent_lower, power_limit); - power_limit *= (100 + od_percent); - power_limit /= 100; - } - *max_power_limit = power_limit; + if (max_power_limit) { + *max_power_limit = power_limit * (100 + od_percent_upper); + *max_power_limit /= 100; } + if (min_power_limit) { + *min_power_limit = power_limit * (100 - od_percent_lower); + *min_power_limit /= 100; + } return 0; } @@ -672,7 +678,7 @@ static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *s uint32_t cur_power_limit; if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) { - sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL); + sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL, NULL); apu_power_limit = metrics_v4->ApuSTAPMLimit; dgpu_power_limit = cur_power_limit; powerRatio = (((apu_power_limit + |