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authorEvan Quan <evan.quan@amd.com>2020-12-07 15:50:08 +0800
committerAlex Deucher <alexander.deucher@amd.com>2021-06-11 16:02:30 -0400
commit1e75be2b674932b53ed1bdd7df35f89e47585388 (patch)
treeebe66004b871fc1f1eba286b5dfcbe413d170652 /drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
parent415e51bdcfa0e724172f66ce12d8ef7819fdd1c7 (diff)
drm/amd/pm: update the cached dpm feature status
For some ASICs, the real dpm feature disablement job is handled by PMFW during baco reset and custom pptable loading. Cached dpm feature status need to be updated to pair that. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h')
-rw-r--r--drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
index c57ce2b2cdc6..9add5f16ff56 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
@@ -79,6 +79,7 @@ int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
uint64_t new_mask);
int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
+ bool no_hw_disablement,
enum smu_feature_mask mask);
int smu_cmn_get_smc_version(struct smu_context *smu,