diff options
| author | Evan Quan <evan.quan@amd.com> | 2020-06-09 14:39:21 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-07-10 17:42:16 -0400 |
| commit | 661b94f5acf7640fd36f807c82f06883901105ad (patch) | |
| tree | b78eb8bc9bd6cc7ca0aad21d600175d8f39f69b2 /drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | |
| parent | b2febc9901ee4bfbcb60ac176cf0b7a4b4e44bc0 (diff) | |
drm/amd/powerplay: put setting hard limit common code in smu_v11_0.c
As designed the common code shared among all smu v11 ASCIs go to
smu_v11_0.c. This helps to maintain clear code layers.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c index 14a30564dbfc..6475639b1fab 100644 --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c @@ -945,7 +945,7 @@ static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu) ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false); if (ret) return ret; - ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq); + ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq); if (ret) return ret; } @@ -1353,7 +1353,7 @@ static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu) } if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { - ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); + ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); if (ret) { dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__); return ret; @@ -1657,9 +1657,9 @@ static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context return 0; if(disable_memory_clock_switch) - ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0); + ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0); else - ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0); + ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0); if(!ret) smu->disable_uclk_switch = disable_memory_clock_switch; |