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authorJiansong Chen <Jiansong.Chen@amd.com>2020-07-21 16:39:38 +0800
committerAlex Deucher <alexander.deucher@amd.com>2020-07-21 15:37:40 -0400
commit85dec7176b96fb6fb44e726ce347db99c572ff64 (patch)
treefbb986de4047540b4b851bc72b1e6063ee74a0ca /drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
parent8985adb69f7dd60afa77c03b9e362ac859347ec5 (diff)
drm/amd/powerplay: retrieve VCN dpm table per instances
To accommodate VCN instances variance, otherwise it may trigger smu response error for configuration with less instances. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c')
-rw-r--r--drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c67
1 files changed, 37 insertions, 30 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 87eedd7c28ec..c162872c3907 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -525,6 +525,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
struct smu_11_0_dpm_table *dpm_table;
+ struct amdgpu_device *adev = smu->adev;
int ret = 0;
/* socclk dpm table setup */
@@ -618,21 +619,24 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
}
/* vclk1 dpm table setup */
- dpm_table = &dpm_context->dpm_tables.vclk1_table;
- if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
- ret = smu_v11_0_set_single_dpm_table(smu,
- SMU_VCLK1,
- dpm_table);
- if (ret)
- return ret;
- dpm_table->is_fine_grained =
- !driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
- } else {
- dpm_table->count = 1;
- dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
- dpm_table->dpm_levels[0].enabled = true;
- dpm_table->min = dpm_table->dpm_levels[0].value;
- dpm_table->max = dpm_table->dpm_levels[0].value;
+ if (adev->vcn.num_vcn_inst > 1) {
+ dpm_table = &dpm_context->dpm_tables.vclk1_table;
+ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_VCLK1,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value =
+ smu->smu_table.boot_values.vclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
}
/* dclk0 dpm table setup */
@@ -654,21 +658,24 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
}
/* dclk1 dpm table setup */
- dpm_table = &dpm_context->dpm_tables.dclk1_table;
- if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
- ret = smu_v11_0_set_single_dpm_table(smu,
- SMU_DCLK1,
- dpm_table);
- if (ret)
- return ret;
- dpm_table->is_fine_grained =
- !driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
- } else {
- dpm_table->count = 1;
- dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
- dpm_table->dpm_levels[0].enabled = true;
- dpm_table->min = dpm_table->dpm_levels[0].value;
- dpm_table->max = dpm_table->dpm_levels[0].value;
+ if (adev->vcn.num_vcn_inst > 1) {
+ dpm_table = &dpm_context->dpm_tables.dclk1_table;
+ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_DCLK1,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value =
+ smu->smu_table.boot_values.dclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
}
/* dcefclk dpm table setup */