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authorRoy Sun <Roy.Sun@amd.com>2021-07-22 13:55:42 +0800
committerAlex Deucher <alexander.deucher@amd.com>2021-07-23 10:09:40 -0400
commitfe6b1032b23eac106292f57330dd4dc64124ef81 (patch)
tree3b7575922b100fdc8a3272f2cde824c9c5c5b0b2 /drivers/gpu/drm/amd
parent7a69ce40aeef448338b313d7a3ee21d2baf24c94 (diff)
drm/amdgpu: Change the imprecise output
The fail reason is that the vfgate is disabled Signed-off-by: Roy Sun <Roy.Sun@amd.com> Reviewed-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 9f3d82dfb79c..f94ef15b3166 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -56,7 +56,7 @@
#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 1
#define GFX10_MEC_HPD_SIZE 2048
-#define RLCG_INTERFACE_NOT_ENABLED 0x4000000
+#define RLCG_VFGATE_DISABLED 0x4000000
#define RLCG_WRONG_OPERATION_TYPE 0x2000000
#define RLCG_NOT_IN_RANGE 0x1000000
@@ -1571,8 +1571,8 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
if (i >= retries) {
if (RLCG_ERROR_REPORT_ENABLED(adev)) {
- if (tmp & RLCG_INTERFACE_NOT_ENABLED)
- pr_err("The interface is not enabled, program reg:0x%05x failed!\n", offset);
+ if (tmp & RLCG_VFGATE_DISABLED)
+ pr_err("The vfgate is disabled, program reg:0x%05x failed!\n", offset);
else if (tmp & RLCG_WRONG_OPERATION_TYPE)
pr_err("Wrong operation type, program reg:0x%05x failed!\n", offset);
else if (tmp & RLCG_NOT_IN_RANGE)