diff options
| author | Yongqiang Sun <yongqiang.sun@amd.com> | 2020-03-05 13:41:43 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-03-19 00:03:04 -0400 |
| commit | 0aa63a333ddf39b180c789c995de5319122116a0 (patch) | |
| tree | b0b125d6439dd18b08511b18eaf92ed1ad4d4e9b /drivers/gpu/drm/amd | |
| parent | 18952c8e5fa420d077f731a9cacaa351061d8015 (diff) | |
drm/amd/display: combine watermark change and clock change for update clocks.
[Why]
underflow happened when playing video on 1366x768 + 4K clone mode due to
incorrect handle watermark change flag and lower down clocks to early.
[How]
Check watermark change flag when decide doing optimized, and check
optimized required flag to do clock update.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc.c | 13 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 |
3 files changed, 10 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 137180ad6a25..2ffb22177df9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1365,7 +1365,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) int i; struct dc_state *context = dc->current_state; - if ((!dc->clk_optimized_required && !dc->wm_optimized_required) || dc->optimize_seamless_boot_streams > 0) + if ((!dc->optimized_required) || dc->optimize_seamless_boot_streams > 0) return true; post_surface_trace(dc); @@ -1379,7 +1379,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) dc->hwss.optimize_bandwidth(dc, context); - dc->clk_optimized_required = false; + dc->optimized_required = false; dc->wm_optimized_required = false; return true; @@ -1828,11 +1828,12 @@ enum surface_update_type dc_check_update_surfaces_for_stream( // If there's an available clock comparator, we use that. if (dc->clk_mgr->funcs->are_clock_states_equal) { if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk)) - dc->clk_optimized_required = true; + dc->optimized_required = true; // Else we fallback to mem compare. } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) { - dc->clk_optimized_required = true; - } + dc->optimized_required = true; + } else if (dc->wm_optimized_required) + dc->optimized_required = true; } return type; @@ -2204,7 +2205,7 @@ static void commit_planes_for_stream(struct dc *dc, dc->optimize_seamless_boot_streams--; if (dc->optimize_seamless_boot_streams == 0) - dc->clk_optimized_required = true; + dc->optimized_required = true; } } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 6cfb534e56bc..d3ceb39e428e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -521,7 +521,7 @@ struct dc { struct dce_hwseq *hwseq; /* Require to optimize clocks and bandwidth for added/removed planes */ - bool clk_optimized_required; + bool optimized_required; bool wm_optimized_required; /* Require to maintain clocks and bandwidth for UEFI enabled HW */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index dad732bb34d5..9cc3314966bd 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1048,7 +1048,7 @@ void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx) if (opp != NULL) opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; - dc->clk_optimized_required = true; + dc->optimized_required = true; if (hubp->funcs->hubp_disconnect) hubp->funcs->hubp_disconnect(hubp); @@ -1099,7 +1099,7 @@ void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) false); hubp->power_gated = true; - dc->clk_optimized_required = false; /* We're powering off, no need to optimize */ + dc->optimized_required = false; /* We're powering off, no need to optimize */ hws->funcs.plane_atomic_power_down(dc, pipe_ctx->plane_res.dpp, |