diff options
| author | Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> | 2024-01-31 08:49:41 +0530 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-02-07 18:14:56 -0500 |
| commit | 66951d98d9bf45ba25acf37fe0747253fafdf298 (patch) | |
| tree | 7c4fd0bd9615f1dca03efcf44482815056588e24 /drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c | |
| parent | e96fddb32931d007db12b1fce9b5e8e4c080401b (diff) | |
drm/amd/display: Add NULL test for 'timing generator' in 'dcn21_set_pipe()'
In "u32 otg_inst = pipe_ctx->stream_res.tg->inst;"
pipe_ctx->stream_res.tg could be NULL, it is relying on the caller to
ensure the tg is not NULL.
Fixes: 474ac4a875ca ("drm/amd/display: Implement some asic specific abm call backs.")
Cc: Yongqiang Sun <yongqiang.sun@amd.com>
Cc: Anthony Koo <Anthony.Koo@amd.com>
Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c')
0 files changed, 0 insertions, 0 deletions