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| author | Rex Zhu <Rex.Zhu@amd.com> | 2016-11-11 11:18:07 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2016-11-23 15:08:39 -0500 |
| commit | b02d4081a5260778ec9d20ac1f079c2b503d9943 (patch) | |
| tree | e218336ddad103867d827635c8f7b0bfee576a00 /drivers/gpu/drm/drm_property.c | |
| parent | 58a6a7dd19980087f5bbbcf7fcfc02a90b72de79 (diff) | |
drm/amdgpu: refine cz uvd clock gate logic.
sw clockgate was used on uvd6.0.
when uvd is idle, we gate the uvd clock.
when decode, we ungate the uvd clock.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/drm_property.c')
0 files changed, 0 insertions, 0 deletions