diff options
| author | Sean Paul <seanpaul@chromium.org> | 2017-07-20 16:09:14 -0400 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-07-31 14:24:14 +0200 |
| commit | 6c70faf1b5d32eb7fa868f1730c51698b53ac677 (patch) | |
| tree | 3da23135ac16713621469bb0c2b2679aee254957 /drivers/gpu/drm/drm_scdc_helper.c | |
| parent | 8d0873a2c45c1a44fc2d5f4936fceac9dba33941 (diff) | |
drm: Fix warning when building docs for scdc_helper
Fixes:
../drivers/gpu/drm/drm_scdc_helper.c:203: ERROR: Unexpected indentation.
../drivers/gpu/drm/drm_scdc_helper.c:204: WARNING: Block quote ends without a blank line; unexpected unindent.
Changes in v2:
- Property blockquote TMDS calculations so they look pretty (Daniel)
- Remove duplicate documentation from the header file
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170720200921.36897-1-seanpaul@chromium.org
Diffstat (limited to 'drivers/gpu/drm/drm_scdc_helper.c')
| -rw-r--r-- | drivers/gpu/drm/drm_scdc_helper.c | 33 |
1 files changed, 20 insertions, 13 deletions
diff --git a/drivers/gpu/drm/drm_scdc_helper.c b/drivers/gpu/drm/drm_scdc_helper.c index 3cd96a95736d..7d1b0f011d33 100644 --- a/drivers/gpu/drm/drm_scdc_helper.c +++ b/drivers/gpu/drm/drm_scdc_helper.c @@ -194,19 +194,26 @@ EXPORT_SYMBOL(drm_scdc_set_scrambling); * @adapter: I2C adapter for DDC channel * @set: ret or reset the high clock ratio * - * TMDS clock ratio calculations go like this: - * TMDS character = 10 bit TMDS encoded value - * TMDS character rate = The rate at which TMDS characters are transmitted(Mcsc) - * TMDS bit rate = 10x TMDS character rate - * As per the spec: - * TMDS clock rate for pixel clock < 340 MHz = 1x the character rate - * = 1/10 pixel clock rate - * TMDS clock rate for pixel clock > 340 MHz = 0.25x the character rate - * = 1/40 pixel clock rate - * - * Writes to the TMDS config register over SCDC channel, and: - * sets TMDS clock ratio to 1/40 when set = 1 - * sets TMDS clock ratio to 1/10 when set = 0 + * + * TMDS clock ratio calculations go like this: + * TMDS character = 10 bit TMDS encoded value + * + * TMDS character rate = The rate at which TMDS characters are + * transmitted (Mcsc) + * + * TMDS bit rate = 10x TMDS character rate + * + * As per the spec: + * TMDS clock rate for pixel clock < 340 MHz = 1x the character + * rate = 1/10 pixel clock rate + * + * TMDS clock rate for pixel clock > 340 MHz = 0.25x the character + * rate = 1/40 pixel clock rate + * + * Writes to the TMDS config register over SCDC channel, and: + * sets TMDS clock ratio to 1/40 when set = 1 + * + * sets TMDS clock ratio to 1/10 when set = 0 * * Returns: * True if write is successful, false otherwise. |