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authorAndrzej Hajda <a.hajda@samsung.com>2018-02-02 16:11:22 +0100
committerInki Dae <inki.dae@samsung.com>2018-05-04 09:39:59 +0900
commit2eced8e917b060587fc8ed46df41c364957a5050 (patch)
tree047e2fce2e73d53bc3ac7e47d5f759609bcc486b /drivers/gpu/drm/exynos/regs-mixer.h
parenta02cbe2e34c576cdc5e7846a3cd55245ab81db47 (diff)
drm/exynos/mixer: fix synchronization check in interlaced mode
In case of interlace mode video processor registers and mixer config register must be check to ensure internal state is in sync with shadow registers. This patch fixes page-faults in interlaced mode. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'drivers/gpu/drm/exynos/regs-mixer.h')
-rw-r--r--drivers/gpu/drm/exynos/regs-mixer.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/exynos/regs-mixer.h b/drivers/gpu/drm/exynos/regs-mixer.h
index c311f571bdf9..189cfa2470a8 100644
--- a/drivers/gpu/drm/exynos/regs-mixer.h
+++ b/drivers/gpu/drm/exynos/regs-mixer.h
@@ -47,6 +47,7 @@
#define MXR_MO 0x0304
#define MXR_RESOLUTION 0x0310
+#define MXR_CFG_S 0x2004
#define MXR_GRAPHIC0_BASE_S 0x2024
#define MXR_GRAPHIC1_BASE_S 0x2044