diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-03-03 21:12:03 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-03-21 17:55:04 +0200 |
| commit | 7243867c6f9617c451c763a7751fa743c3f04f4a (patch) | |
| tree | 8366cb27e6ac752abccf0fe3ad10f7d875ff121e /drivers/gpu/drm/i915/display/intel_bw.c | |
| parent | 0d21fd10fb3c7485e4701d9f89bf463965e28339 (diff) | |
drm/i915: Nuke intel_bw_calc_min_cdclk()
intel_bw_calc_min_cdclk() is entirely pointless. All it manages to do is
somehow conflate the per-pipe min cdclk with dbuf min cdclk. There is no
(at least documented) dbuf min cdclk limit on pre-skl so let's just get
rid of all this confusion.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220303191207.27931-6-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_bw.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_bw.c | 49 |
1 files changed, 4 insertions, 45 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 5517d1ac78d6..e991949c6e5d 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -717,7 +717,7 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state, } } -int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) +int intel_bw_calc_min_cdclk(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_bw_state *new_bw_state = NULL; @@ -728,6 +728,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) enum pipe pipe; int i; + if (DISPLAY_VER(dev_priv) < 9) + return 0; + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { new_bw_state = intel_atomic_get_bw_state(state); if (IS_ERR(new_bw_state)) @@ -772,50 +775,6 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) return 0; } -int intel_bw_calc_min_cdclk(struct intel_atomic_state *state) -{ - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - struct intel_bw_state *new_bw_state = NULL; - struct intel_bw_state *old_bw_state = NULL; - const struct intel_crtc_state *crtc_state; - struct intel_crtc *crtc; - int min_cdclk = 0; - enum pipe pipe; - int i; - - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { - new_bw_state = intel_atomic_get_bw_state(state); - if (IS_ERR(new_bw_state)) - return PTR_ERR(new_bw_state); - - old_bw_state = intel_atomic_get_old_bw_state(state); - } - - if (!old_bw_state) - return 0; - - for_each_pipe(dev_priv, pipe) { - struct intel_cdclk_state *cdclk_state; - - cdclk_state = intel_atomic_get_new_cdclk_state(state); - if (!cdclk_state) - return 0; - - min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); - } - - new_bw_state->min_cdclk = min_cdclk; - - if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { - int ret = intel_atomic_lock_global_state(&new_bw_state->base); - - if (ret) - return ret; - } - - return 0; -} - static u16 icl_qgv_points_mask(struct drm_i915_private *i915) { unsigned int num_psf_gv_points = i915->max_bw[0].num_psf_gv_points; |