diff options
| author | Jani Nikula <jani.nikula@intel.com> | 2020-11-30 13:15:54 +0200 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2020-12-01 17:56:02 +0200 |
| commit | 507007fb591b23a0f9ad5ed62e2d60a004410ccb (patch) | |
| tree | 086138f805b6df4ee08723d71ace87c62a987599 /drivers/gpu/drm/i915/display/intel_cdclk.c | |
| parent | 669f3f2bac1ca6ad887419f63ac5430e9ea85e6a (diff) | |
drm/i915/cdclk: prefer intel_de_write() over I915_WRITE()
Let's try to not add new ones while we're phasing out I915_READ() and
I915_WRITE().
Fixes: 27a6bc802bd9 ("drm/i915/dg1: Initialize RAWCLK properly")
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201130111601.2817-3-jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_cdclk.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cdclk.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index c449d28d0560..088d5908176c 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2710,8 +2710,8 @@ static int dg1_rawclk(struct drm_i915_private *dev_priv) * DG1 always uses a 38.4 MHz rawclk. The bspec tells us * "Program Numerator=2, Denominator=4, Divider=37 decimal." */ - I915_WRITE(PCH_RAWCLK_FREQ, - CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); + intel_de_write(dev_priv, PCH_RAWCLK_FREQ, + CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); return 38400; } |