diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-02-14 00:52:50 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-02-17 23:25:15 +0200 |
| commit | 3eb08ea58e5717cf758b9eff6d9604aa3525ab94 (patch) | |
| tree | f3dbad3b13d793f0fb6924dce01595c19298cbde /drivers/gpu/drm/i915/display/intel_drrs.c | |
| parent | 5ac421a9ec6668369b7910d4b1e7f5e7e9e9ec94 (diff) | |
drm/i915: s/PIPECONF/TRANSCONF/
Rename PIPECONF to TRANSCONF to make it clear what it actually
applies to.
While the usual convention is to pick the earliers name I think
in this case it's more clear to use the later name. Especially
as even the register offset is in the wrong range (0x70000 vs.
0x60000) and thus makes it look like this is per-pipe.
There is one place in gvt that's doing something with TRANSCONF
while iterating with for_each_pipe(). So that might not be doing
the right thing for TRANSCODER_EDP, dunno. Not knowing what it
does I left it as is to avoid breakage.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230213225258.2127-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_drrs.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_drrs.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c index 241ad4477c39..760e63cdc0c8 100644 --- a/drivers/gpu/drm/i915/display/intel_drrs.c +++ b/drivers/gpu/drm/i915/display/intel_drrs.c @@ -71,11 +71,11 @@ intel_drrs_set_refresh_rate_pipeconf(struct intel_crtc *crtc, u32 bit; if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - bit = PIPECONF_REFRESH_RATE_ALT_VLV; + bit = TRANSCONF_REFRESH_RATE_ALT_VLV; else - bit = PIPECONF_REFRESH_RATE_ALT_ILK; + bit = TRANSCONF_REFRESH_RATE_ALT_ILK; - intel_de_rmw(dev_priv, PIPECONF(cpu_transcoder), + intel_de_rmw(dev_priv, TRANSCONF(cpu_transcoder), bit, refresh_rate == DRRS_REFRESH_RATE_LOW ? bit : 0); } |