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authorVille Syrjälä <ville.syrjala@linux.intel.com>2022-01-28 12:37:53 +0200
committerVille Syrjälä <ville.syrjala@linux.intel.com>2022-02-01 11:33:23 +0200
commit1d06c820b2b7ceb38bdf0775fac495db4ad4d10e (patch)
tree91a755bbd328d06db47d352f6566c643be5c9d36 /drivers/gpu/drm/i915/display/intel_drrs.c
parent6d6c932daef5c5b3cd5e3692e79507d2a3306031 (diff)
drm/i915: Clear DP M2/N2 when not doing DRRS
Make life simpler by always programming DP M2/N2 with a consistent value. This will lets use do state readout+chec unconditionally. I was first going to just set M2/N2=M1/N1 but then it occurred to me that it might interfere with fastboot on account of BIOS likely leaving the registers zeroed. So let's zero out the values instead (except TU where a zero register value actually means '1'). Still not sure that's the best approach but lets go with it for now. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220128103757.22461-14-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_drrs.c')
-rw-r--r--drivers/gpu/drm/i915/display/intel_drrs.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index 3515f1700838..fa715b8ea310 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -74,10 +74,14 @@ intel_drrs_compute_config(struct intel_dp *intel_dp,
int output_bpp, bool constant_n)
{
struct intel_connector *connector = intel_dp->attached_connector;
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
int pixel_clock;
- if (!can_enable_drrs(connector, pipe_config))
+ if (!can_enable_drrs(connector, pipe_config)) {
+ if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
+ intel_zero_m_n(&pipe_config->dp_m2_n2);
return;
+ }
pipe_config->has_drrs = true;