diff options
| author | José Roberto de Souza <jose.souza@intel.com> | 2021-06-25 16:56:00 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2021-07-20 16:15:30 -0700 |
| commit | 425057e725934b46760b0386b18bb4eb8ee066a7 (patch) | |
| tree | ec3a78031e49525b1204eaa7bec69f9a6d037a49 /drivers/gpu/drm/i915/display/intel_fbc.c | |
| parent | 36203e4fb4cb7d65dc471493caf132ebd8d263bb (diff) | |
drm/i915/display: Disable FBC when PSR2 is enabled display 12 and newer
This is now a requirement for all display 12 and newer, not only for
tigerlake.
BSpec: 50422
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210625235600.765677-2-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_fbc.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_fbc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 82effb64a3b9..ddfc17e21668 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -912,11 +912,11 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) } /* - * Tigerlake is not supporting FBC with PSR2. + * Display 12+ is not supporting FBC with PSR2. * Recommendation is to keep this combination disabled * Bspec: 50422 HSD: 14010260002 */ - if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) { + if (fbc->state_cache.psr2_active && DISPLAY_VER(dev_priv) >= 12) { fbc->no_fbc_reason = "not supported with PSR2"; return false; } |