diff options
| author | Uma Shankar <uma.shankar@intel.com> | 2020-12-02 00:34:06 +0530 |
|---|---|---|
| committer | Uma Shankar <uma.shankar@intel.com> | 2020-12-02 19:08:34 +0530 |
| commit | f9c914a5b946e3e85fff939ebb7e36057b0c410d (patch) | |
| tree | 77b9c4dcc92e6a688befb639b2bca6db6bcfe653 /drivers/gpu/drm/i915/display/intel_fbc.c | |
| parent | 91bd7a441bf03f87fca72517541aa6e79909a624 (diff) | |
Revert "drm/i915/display/fbc: Disable fbc by default on TGL"
FBC can be re-enabled on TGL with WA of keeping it disabled
while PSR2 is enabled.
This reverts commit 2982ded2ff5ce0cf1a49bc39a526da182782b664.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201201190406.1752-3-uma.shankar@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_fbc.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_fbc.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index f5d5a648cb22..33200b5cfad0 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1445,13 +1445,6 @@ static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv) if (!HAS_FBC(dev_priv)) return 0; - /* - * Fbc is causing random underruns in CI execution on TGL platforms. - * Disabling the same while the problem is being debugged and analyzed. - */ - if (IS_TIGERLAKE(dev_priv)) - return 0; - if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) return 1; |