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| author | Matt Roper <matthew.d.roper@intel.com> | 2023-02-13 16:19:06 -0800 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2023-02-23 13:52:33 +0200 |
| commit | 33c25354939099b76ecb6c82d1c7c50400fbcca6 (patch) | |
| tree | 974543d5f65ac2fd73e99cc350ad325be5d8a910 /drivers/gpu/drm/i915/display/intel_quirks.c | |
| parent | 8038510b1fe443ffbc0e356db5f47cbb8678a594 (diff) | |
drm/i915/xelpmp: Consider GSI offset when doing MCR lookups
MCR range tables use the final MMIO offset of a register (including the
0x380000 GSI offset when applicable). Since the i915_mcr_reg_t passed
as a parameter during steering lookup does not include the GSI offset,
we need to add it back in for GSI registers before searching the tables.
Fixes: a7ec65fc7e83 ("drm/i915/xelpmp: Add multicast steering for media GT")
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230214001906.1477370-1-matthew.d.roper@intel.com
(cherry picked from commit d6683bbe70d4cdbf3da6acecf7d569cc6f0b4382)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_quirks.c')
0 files changed, 0 insertions, 0 deletions