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author | Matt Roper <matthew.d.roper@intel.com> | 2022-06-01 08:07:22 -0700 |
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committer | Matt Roper <matthew.d.roper@intel.com> | 2022-06-02 07:19:14 -0700 |
commit | 4cfd16659641067f618cdd3589eda42eb2943399 (patch) | |
tree | 6c077930db6d3c44309af7fa3747c67f960d758d /drivers/gpu/drm/i915/gt/gen8_ppgtt.h | |
parent | aa2bdc4843f5871e6c68fbec5e10c0dbaf10ff91 (diff) |
drm/i915/sseu: Simplify gen11+ SSEU handling
Although gen11 and gen12 architectures supported the concept of multiple
slices, in practice all the platforms that were actually designed only
had a single slice (i.e., note the parameters to 'intel_sseu_set_info'
that we pass for each platform). We can simplify the code slightly by
dropping the multi-slice logic from gen11+ platforms.
v2:
- Promote drm_dbg to drm_WARN_ON if the slice fuse register reports
unexpected fusing. (Tvrtko)
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220601150725.521468-4-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/gen8_ppgtt.h')
0 files changed, 0 insertions, 0 deletions