diff options
| author | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2020-04-23 21:23:52 +0300 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2020-04-24 00:52:14 +0100 |
| commit | b4892e44043235368dfc714f4a6530f6793802b0 (patch) | |
| tree | 3506a23d3eb9358dba593fd0b3b479fb8c32e2c0 /drivers/gpu/drm/i915/gt/intel_context_sseu.c | |
| parent | f1cc6acf22dd7b2a3548fa5dd9537b90a44668b5 (diff) | |
drm/i915: Make define for lrc state offset
More often than not, we need a byte offset into lrc
register state from the start of the hw state. Make it so.
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200423182355.21837-3-mika.kuoppala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_context_sseu.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_context_sseu.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c b/drivers/gpu/drm/i915/gt/intel_context_sseu.c index 57a30956c922..487299cb91f2 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c @@ -25,8 +25,7 @@ static int gen8_emit_rpcs_config(struct i915_request *rq, return PTR_ERR(cs); offset = i915_ggtt_offset(ce->state) + - LRC_STATE_PN * PAGE_SIZE + - CTX_R_PWR_CLK_STATE * 4; + LRC_STATE_OFFSET + CTX_R_PWR_CLK_STATE * 4; *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; *cs++ = lower_32_bits(offset); |