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authorLucas De Marchi <lucas.demarchi@intel.com>2021-07-22 17:25:51 -0700
committerLucas De Marchi <lucas.demarchi@intel.com>2021-07-26 08:15:18 -0700
commit816753c06f23773c83763cfef3ded32a387e54e1 (patch)
tree081d538d1388839590e2a4a04ce5d968771c83f9 /drivers/gpu/drm/i915/gt/intel_engine_types.h
parentbfac1e2b6e2d6b3fdb3d8f997187d6f1c63ea965 (diff)
drm/i915/gt: nuke gen6_hw_id
This is only used by GRAPHICS_VER == 6 and GRAPHICS_VER == 7. All other recent platforms do not depend on this field, so it doesn't make much sense to keep it generic like that. Instead, just do a mapping from engine class to HW ID in the single place that is needed. v2: use macros with the direct register address instead of calculating from the legacy HW_ID (Matt Roper) Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210723002551.3906535-1-lucas.demarchi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_engine_types.h')
-rw-r--r--drivers/gpu/drm/i915/gt/intel_engine_types.h10
1 files changed, 1 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 8f1f2f12d6f5..3f308a920b50 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -28,14 +28,7 @@
#include "intel_wakeref.h"
#include "intel_workarounds_types.h"
-/* Legacy HW Engine ID */
-
-#define RCS0_HW 0
-#define VCS0_HW 1
-#define BCS0_HW 2
-#define VECS0_HW 3
-
-/* Gen11+ HW Engine class + instance */
+/* HW Engine class + instance */
#define RENDER_CLASS 0
#define VIDEO_DECODE_CLASS 1
#define VIDEO_ENHANCEMENT_CLASS 2
@@ -274,7 +267,6 @@ struct intel_engine_cs {
intel_engine_mask_t mask;
- u8 gen6_hw_id;
u8 class;
u8 instance;