diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2022-06-01 08:07:25 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2022-06-02 07:21:09 -0700 |
| commit | 5ac342ef84d7dccd1ba43f5fa2dc10a6feda91e2 (patch) | |
| tree | 2646fb6d3c518a2bbda388e9b5e3d61a0b2c9a45 /drivers/gpu/drm/i915/gt/intel_sseu.h | |
| parent | b87d39019651c9cae169396cf5ae525393084490 (diff) | |
drm/i915/pvc: Add SSEU changes
PVC splits the mask of enabled DSS over two registers. It also changes
the meaning of the EU fuse register such that each bit represents a
single EU rather than a pair of EUs.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220601150725.521468-7-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_sseu.h')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_sseu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h index f0e09b743faa..aa87d3832d60 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.h +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h @@ -33,7 +33,7 @@ struct drm_printer; * Maximum number of 32-bit registers used by hardware to express the * enabled/disabled subslices. */ -#define I915_MAX_SS_FUSE_REGS 1 +#define I915_MAX_SS_FUSE_REGS 2 #define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32) /* Maximum number of EUs that can exist within a subslice or DSS. */ |