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authorZhi Wang <zhi.a.wang@intel.com>2016-04-25 18:28:56 -0400
committerZhenyu Wang <zhenyuw@linux.intel.com>2016-10-14 18:13:06 +0800
commit04d348ae3f0aea6523bc3b0688b5fc90c1c60d0e (patch)
tree1eadc499b3da6b57f1bebed7b81f77a79b9a8144 /drivers/gpu/drm/i915/gvt/gvt.h
parente39c5add322184de3be052d438dfd24375bfeaea (diff)
drm/i915/gvt: vGPU display virtualization
This patch introduces the GVT-g display virtualization. It consists a collection of display MMIO handlers, like power well register handler, pipe register handler, plane register handler, which will emulate all display MMIOs behavior to support virtual mode setting sequence for guest. Signed-off-by: Bing Niu <bing.niu@intel.com> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/gvt.h')
-rw-r--r--drivers/gpu/drm/i915/gvt/gvt.h30
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 2560c3aaac45..1619881dbd51 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -39,6 +39,8 @@
#include "reg.h"
#include "interrupt.h"
#include "gtt.h"
+#include "display.h"
+#include "edid.h"
#define GVT_MAX_VGPU 8
@@ -105,8 +107,12 @@ struct intel_vgpu_cfg_space {
#define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
+#define INTEL_GVT_MAX_PIPE 4
+
struct intel_vgpu_irq {
bool irq_warn_once[INTEL_GVT_EVENT_MAX];
+ DECLARE_BITMAP(flip_done_event[INTEL_GVT_MAX_PIPE],
+ INTEL_GVT_EVENT_MAX);
};
struct intel_vgpu_opregion {
@@ -117,6 +123,14 @@ struct intel_vgpu_opregion {
#define vgpu_opregion(vgpu) (&(vgpu->opregion))
+#define INTEL_GVT_MAX_PORT 5
+
+struct intel_vgpu_display {
+ struct intel_vgpu_i2c_edid i2c_edid;
+ struct intel_vgpu_port ports[INTEL_GVT_MAX_PORT];
+ struct intel_vgpu_sbi sbi;
+};
+
struct intel_vgpu {
struct intel_gvt *gvt;
int id;
@@ -131,6 +145,7 @@ struct intel_vgpu {
struct intel_vgpu_irq irq;
struct intel_vgpu_gtt gtt;
struct intel_vgpu_opregion opregion;
+ struct intel_vgpu_display display;
};
struct intel_gvt_gm {
@@ -175,8 +190,23 @@ struct intel_gvt {
struct intel_gvt_irq irq;
struct intel_gvt_gtt gtt;
struct intel_gvt_opregion opregion;
+
+ struct task_struct *service_thread;
+ wait_queue_head_t service_thread_wq;
+ unsigned long service_request;
};
+enum {
+ INTEL_GVT_REQUEST_EMULATE_VBLANK = 0,
+};
+
+static inline void intel_gvt_request_service(struct intel_gvt *gvt,
+ int service)
+{
+ set_bit(service, (void *)&gvt->service_request);
+ wake_up(&gvt->service_thread_wq);
+}
+
void intel_gvt_free_firmware(struct intel_gvt *gvt);
int intel_gvt_load_firmware(struct intel_gvt *gvt);