diff options
| author | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2016-04-13 17:26:43 +0300 |
|---|---|---|
| committer | Mika Kuoppala <mika.kuoppala@intel.com> | 2016-04-14 12:27:37 +0300 |
| commit | 3accaf7e734d691dd8494548da009a646426655c (patch) | |
| tree | 542e62b70c5da5f1cd6f7023e0799042bcfb88f2 /drivers/gpu/drm/i915/i915_gem_gtt.c | |
| parent | 666fbcf5c21d8d8654b00b9c2e21a3caf070e9f8 (diff) | |
drm/i915: Store and use edram capabilities
Store the edram capabilities instead of only the size of
edram. This is preparatory patch to allow edram size calculation
based on edram capability bits for gen9+. With gen9 the
edram is behind llc and is a separate entity. With hsw/bdw
it was more of a victim cache for LLC so the name 'eLLC' might
be warranted. Regardless, rename all mentions of eLLC to EDRAM to
clear the confusion.
v2: return bytes for edram size (Chris)
s/eLLC/eDRAM in output if we are gen > 8
v3: rebase, INTEL_GEN (Chris)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_gtt.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_gtt.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index c5cb04907525..9f165feb54ae 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -3172,7 +3172,8 @@ int i915_ggtt_init_hw(struct drm_device *dev) } else if (INTEL_INFO(dev)->gen < 8) { ggtt->probe = gen6_gmch_probe; ggtt->base.cleanup = gen6_gmch_remove; - if (IS_HASWELL(dev) && dev_priv->ellc_size) + + if (HAS_EDRAM(dev)) ggtt->base.pte_encode = iris_pte_encode; else if (IS_HASWELL(dev)) ggtt->base.pte_encode = hsw_pte_encode; |