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authorarun.siluvery@linux.intel.com <arun.siluvery@linux.intel.com>2016-06-06 09:52:49 +0100
committerTvrtko Ursulin <tvrtko.ursulin@intel.com>2016-06-06 13:04:37 +0100
commit6bb6285582e0cf9b3a8440e0e714aae5f66d9ce2 (patch)
tree234fd5c81fab63b444e9ebcc473f876aaeee9c51 /drivers/gpu/drm/i915/i915_reg.h
parent14bb2c11796d70bf20b92fa4a1459743c6afecb2 (diff)
drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear
Kernel only need to add a register to HW whitelist, required for a preemption related issue. Reference: HSD#2131039 Reviewed-by: Jeff McGee <jeff.mcgee@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1465203169-16591-1-git-send-email-arun.siluvery@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f7b822a86915..04a3fd277ab3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6072,6 +6072,7 @@ enum skl_disp_power_wells {
#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
+#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
/* GEN7 chicken */