diff options
| author | Imre Deak <imre.deak@intel.com> | 2019-05-09 20:34:44 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2019-05-14 14:06:30 +0300 |
| commit | 08d8e17005a34f773f55005a153edc28fc5ab5e3 (patch) | |
| tree | 7c5ebabc61185e30c0ba509abbbd070f6b4b0171 /drivers/gpu/drm/i915/intel_display.c | |
| parent | 6f08ebe779a3e5bec8ee3a14b9c15329a59221b1 (diff) | |
drm/i915: Replace use of PLLS power domain with DISPLAY_CORE domain
There isn't a separate power domain specific to PLLs. When programming
them we require the same power domain to be enabled which is needed when
accessing other display core parts (not specific to any
pipe/port/transcoder). This corresponds to the DISPLAY_CORE domain added
previously in this patchset, so use that instead to save bits in the
power domain mask.
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190509173446.31095-10-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8f3c3894e11d..b53676e558cb 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6363,7 +6363,7 @@ static u64 get_crtc_power_domains(struct drm_crtc *crtc, mask |= BIT_ULL(POWER_DOMAIN_AUDIO); if (crtc_state->shared_dpll) - mask |= BIT_ULL(POWER_DOMAIN_PLLS); + mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE); return mask; } |