diff options
| author | Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> | 2017-09-18 15:21:41 -0700 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2017-09-25 15:22:07 +0300 |
| commit | 3bc31a7f4d376083b972acdc1a580e05c3a6dc12 (patch) | |
| tree | 71d87f624c946f1603ce62ceee07342290afbc89 /drivers/gpu/drm/i915/intel_dp.c | |
| parent | e8b2577c5e312d175ed11a35a12346b19059277d (diff) | |
drm/i915/dp: Remove useless debug about TPS3 support
We already print training pattern used during link training and also
print if the source or sink does not support TPS3 for HBR2 link rates,
see intel_dp_training_pattern().
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170918222141.4674-5-dhinakaran.pandiyan@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index ff04b3616f95..90e756c76f10 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -4753,10 +4753,6 @@ intel_dp_long_pulse(struct intel_connector *intel_connector) if (intel_encoder->type != INTEL_OUTPUT_EDP) intel_encoder->type = INTEL_OUTPUT_DP; - DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", - yesno(intel_dp_source_supports_hbr2(intel_dp)), - yesno(drm_dp_tps3_supported(intel_dp->dpcd))); - if (intel_dp->reset_link_params) { /* Initial max link lane count */ intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); |