diff options
| author | Jani Nikula <jani.nikula@intel.com> | 2016-09-16 16:59:44 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2016-09-26 12:08:22 +0300 |
| commit | a117f378f44150e6d13d2f19740fb757425b651f (patch) | |
| tree | 01f8731e41d4fb41347fcbd46c0c6d11267bcd80 /drivers/gpu/drm/i915/intel_dp_link_training.c | |
| parent | 4c0b8a8bc49c477be9467f614b6b4ec479736019 (diff) | |
drm/i915/skl: drop workarounds for A0 and B0 revisions
Pre-production hardware is not supported.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/7929af62a68504c84038a8db1625bd96ebaa9e6f.1474034059.git.jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp_link_training.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp_link_training.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c index c438b02184cb..0048b520baf7 100644 --- a/drivers/gpu/drm/i915/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c @@ -225,9 +225,6 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp) * Intel platforms that support HBR2 also support TPS3. TPS3 support is * also mandatory for downstream devices that support HBR2. However, not * all sinks follow the spec. - * - * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is - * supported in source but still not enabled. */ source_tps3 = intel_dp_source_supports_hbr2(intel_dp); sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd); |