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authorVille Syrjälä <ville.syrjala@linux.intel.com>2018-01-30 22:38:02 +0200
committerVille Syrjälä <ville.syrjala@linux.intel.com>2018-02-20 20:44:44 +0200
commitc154d1e0aabf77212a49f0cf3d54eecb0ae395a4 (patch)
tree448bb74868bc3038d5101704e95194178f0c94d9 /drivers/gpu/drm/i915/intel_pm.c
parent32ea06b67eb2b693c78bd795b8a8f7fdac03fb6a (diff)
drm/i915: Set the primary plane pipe select bits on gen4
i965 and g4x still have the pipe select bits in the plane control registers, they're just hardcoded to select a specific pipe. However plane C on i965 can still move between the pipes, thus we should program the pipe select bits on i965 if we want to expose plane C some day. Since there is no harm in programming the bits on any plane on i965/g4x let's just always set them. This will also make our pre-computed register value match what the hardware register would read, should we want to cross check the two. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180130203807.13721-2-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
0 files changed, 0 insertions, 0 deletions