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| author | Imre Deak <imre.deak@intel.com> | 2015-01-25 13:27:11 -0800 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-04-14 13:55:20 +0200 |
| commit | 9647ff36ae266b74c82780f7f4e3bb4a39506107 (patch) | |
| tree | 3c695b9e00338d375d1f581af224ea518dfa5819 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 1c046bc1db49e5a42e5c4167ac42cee4c1725a37 (diff) | |
drm/i915/gen9: fix PIPE_CONTROL flush for VS_INVALIDATE
On GEN9+ per specification a NULL PIPE_CONTROL needs to be emitted
before any PIPE_CONTROL command with the VS_INVALIDATE flag set.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
0 files changed, 0 insertions, 0 deletions