diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2018-12-28 17:16:37 +0000 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2018-12-31 15:35:45 +0000 |
| commit | 2f0c733b353c2bf6175a4b3cc7d8fb66e86d69f0 (patch) | |
| tree | 469dfff4ba2a80dcf001647e0741c73f7743305a /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | ed2922c025c3fd208e0fe7589f587ba37e1a4834 (diff) | |
drm/i915/ringbuffer: Remove irq-seqno w/a for gen6/7 rcs
Having transitioned to using PIPECONTROL to combine the flush with the
breadcrumb write using their post-sync functions, assume that this will
resolve the serialisation with the subsequent MI_USER_INTERRUPT. That is
when inspecting the breadcrumb after an interrupt we can rely on the write
being posted (i.e. the HWSP will be coherent).
Testing using gem_sync shows that the PIPECONTROL + CS stall does
serialise the command streamer sufficient that the breadcrumb lands
before the MI_USER_INTERRUPT. The same is not true for MI_FLUSH_DW.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181228171641.16531-2-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index d773f7dd32a9..1b9264883a8d 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2218,13 +2218,11 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine) engine->emit_flush = gen7_render_ring_flush; engine->emit_breadcrumb = gen7_rcs_emit_breadcrumb; engine->emit_breadcrumb_sz = gen7_rcs_emit_breadcrumb_sz; - engine->irq_seqno_barrier = gen6_seqno_barrier; } else if (IS_GEN(dev_priv, 6)) { engine->init_context = intel_rcs_ctx_init; engine->emit_flush = gen6_render_ring_flush; engine->emit_breadcrumb = gen6_rcs_emit_breadcrumb; engine->emit_breadcrumb_sz = gen6_rcs_emit_breadcrumb_sz; - engine->irq_seqno_barrier = gen6_seqno_barrier; } else if (IS_GEN(dev_priv, 5)) { engine->emit_flush = gen4_render_ring_flush; } else { |