diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2021-09-10 13:10:30 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-09-21 17:16:27 -0700 |
| commit | c74e66d47e883d7fa345a74154d355a297b1abbd (patch) | |
| tree | 516821111d0c9036b68f4eb9a361d2f3f16892ff /drivers/gpu/drm/i915/selftests | |
| parent | e5b32ae34b02c74d3327789281b88c1e59fdca30 (diff) | |
drm/i915/dg2: Add DG2-specific shadow register table
We thought the DG2 table of shadowed registers would be the same as the
gen12/xehp table, but it turns out that there are a few minor
differences that require us to define a new DG2-specific table:
* One register is removed (0xC4D4)
* One register is added (0xC4E0)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210910201030.3436066-7-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/selftests')
| -rw-r--r-- | drivers/gpu/drm/i915/selftests/intel_uncore.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c index 22ef2c87df1a..bc8128170a99 100644 --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c @@ -68,6 +68,7 @@ static int intel_shadow_table_check(void) { gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) }, { gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) }, { gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs) }, + { dg2_shadowed_regs, ARRAY_SIZE(dg2_shadowed_regs) }, }; const struct i915_range *range; unsigned int i, j; |