diff options
| author | Imre Deak <imre.deak@intel.com> | 2024-04-17 01:10:04 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2024-04-19 17:20:53 +0300 |
| commit | e54cc6deecceb83d4cd004dc37f0f099c14f82ea (patch) | |
| tree | bf2af95a653907d927819674fc1b42e97070d17a /drivers/gpu/drm/i915 | |
| parent | fd13841d8b2e8b619f542ed75950c3b206605340 (diff) | |
drm/i915/dp_mst: Account with the DSC DPT bpp limit on MTL
The DPT/DSC bpp limit should be accounted for on MTL platforms as well,
do so.
Bspec: 49259
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240416221010.376865-6-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 350532c011ac..836f28f70d73 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -56,7 +56,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp struct intel_crtc_state *crtc_state, bool dsc) { - if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) { + if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 20 && dsc) { int output_bpp = bpp; int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); /* |