diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2020-03-11 09:22:58 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2020-03-13 09:02:21 -0700 |
| commit | 14f49be483b57911f1b9733d1ea2f4d920968418 (patch) | |
| tree | 0de8e581e58d177b432843e38d5cf318a47fdb1d /drivers/gpu/drm/i915 | |
| parent | d0ed510a8eb12915aedf1cdc28bd1707fbe6c9c0 (diff) | |
drm/i915: Add Wa_1406306137:icl,ehl
v2:
- Move to context workarounds. ROW_CHICKEN4 is part of the context
image on gen11 (although it isn't on gen12).
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200311162300.1838847-5-matthew.d.roper@intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 3bbd89294279..2318b55b9722 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -581,6 +581,9 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER, 0, /* write-only register; skip validation */ 0xFFFFFFFF); + + /* Wa_1406306137:icl,ehl */ + wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); } static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b6b52b735120..309cb7d96b35 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9151,6 +9151,7 @@ enum { #define GEN9_ROW_CHICKEN4 _MMIO(0xe48c) #define GEN12_DISABLE_TDL_PUSH REG_BIT(9) +#define GEN11_DIS_PICK_2ND_EU REG_BIT(7) #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) |