diff options
| author | Neil Armstrong <narmstrong@baylibre.com> | 2017-04-04 14:15:25 +0200 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2017-04-04 17:49:31 +0200 |
| commit | 2f4c95dc3d1d1518cb6a5e280050c48a79d3ee08 (patch) | |
| tree | 7cb26b6c02db1737985130d3736b415ffe557647 /drivers/gpu/drm/meson/meson_vclk.h | |
| parent | cb110b665e77ebf99f8235f257b88eea007186d3 (diff) | |
drm/meson: add support for HDMI clock support
This patchs adds support for the supported HDMI modes clocks frequencies.
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers/gpu/drm/meson/meson_vclk.h')
| -rw-r--r-- | drivers/gpu/drm/meson/meson_vclk.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/meson/meson_vclk.h b/drivers/gpu/drm/meson/meson_vclk.h index ec62735996de..0401b5213471 100644 --- a/drivers/gpu/drm/meson/meson_vclk.h +++ b/drivers/gpu/drm/meson/meson_vclk.h @@ -23,12 +23,14 @@ enum { MESON_VCLK_TARGET_CVBS = 0, + MESON_VCLK_TARGET_HDMI = 1, }; /* 27MHz is the CVBS Pixel Clock */ -#define MESON_VCLK_CVBS 27000 +#define MESON_VCLK_CVBS 27000 void meson_vclk_setup(struct meson_drm *priv, unsigned int target, - unsigned int freq); + unsigned int vclk_freq, unsigned int venc_freq, + unsigned int dac_freq, bool hdmi_use_enci); #endif /* __MESON_VCLK_H */ |