diff options
| author | Jordan Crouse <jcrouse@codeaurora.org> | 2019-02-04 09:15:42 -0700 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2019-04-19 11:50:06 -0700 |
| commit | e31fdb74c183a8cfe32dc31974f3d626b3af4393 (patch) | |
| tree | f288b42a8da7749bfefafc112e430d2424eab3e5 /drivers/gpu/drm/msm/adreno/a6xx_gmu.h | |
| parent | 9325d4266afd4e54ff4aae0018d420d596964126 (diff) | |
drm/msm/a6xx: Make GMU reset useful
Now that the GX domain is sorted we can wire up a working GMU reset.
IF a GMU hang was detected then try to forcefully shut down the GMU
in the power down sequence which should ensure that it can recover
normally on the next power up.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/adreno/a6xx_gmu.h')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index 078d418c8179..c5b1887f259f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -27,9 +27,6 @@ struct a6xx_gmu_bo { /* the GMU is coming up for the first time or back from a power collapse */ #define GMU_COLD_BOOT 1 -/* The GMU is being soft reset after a fault */ -#define GMU_RESET 2 - /* * These define the level of control that the GMU has - the higher the number * the more things that the GMU hardware controls on its own. @@ -79,6 +76,7 @@ struct a6xx_gmu { struct a6xx_hfi_queue queues[2]; struct tasklet_struct hfi_tasklet; + bool hung; }; static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset) |