diff options
| author | Rob Clark <robdclark@chromium.org> | 2023-07-27 14:20:11 -0700 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2023-08-07 14:19:16 -0700 |
| commit | f30a648d87485174700cd91e54fada5df5691a77 (patch) | |
| tree | 109333969a7bc1bd80b3dff53c9a3393999ceaa6 /drivers/gpu/drm/msm/adreno/adreno_device.c | |
| parent | 155668ef412fc82ff3172666831d95770141cdd6 (diff) | |
drm/msm/adreno: Allow SoC specific gpu device table entries
There are cases where there are differences due to SoC integration.
Such as cache-coherency support, and (in the next patch) e-fuse to
speedbin mappings.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549767/
Diffstat (limited to 'drivers/gpu/drm/msm/adreno/adreno_device.c')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/adreno_device.c | 34 |
1 files changed, 30 insertions, 4 deletions
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 3c531da417b9..e62bc895a31f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -259,6 +259,32 @@ static const struct adreno_info gpulist[] = { .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, }, { + .machine = "qcom,sm4350", + .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, + }, { + .machine = "qcom,sm6375", + .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, + }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), .revn = 619, .fw = { @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev) /* identify gpu: */ for (i = 0; i < ARRAY_SIZE(gpulist); i++) { const struct adreno_info *info = &gpulist[i]; + if (info->machine && !of_machine_is_compatible(info->machine)) + continue; if (adreno_cmp_rev(info->rev, rev)) return info; } @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) config.rev.minor, config.rev.patchid); priv->is_a2xx = config.rev.core == 2; + priv->has_cached_coherent = + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT); gpu = info->init(drm); if (IS_ERR(gpu)) { @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) if (ret) return ret; - priv->has_cached_coherent = - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) && - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu)); - return 0; } |