diff options
| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-01-16 08:33:14 +0200 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-01-21 12:23:25 +0200 |
| commit | e92a4ae1981baecccdc1823e1f10dc8f566df0ad (patch) | |
| tree | bfdea0866260918484dbcd80103ca62d8ee9336e /drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | |
| parent | 00feff8f12747cb12684513d7fd97bb9352b721a (diff) | |
drm/msm/dpu: fix blend setup for DMA4 and DMA5 layers
SM8550 uses new register to map SSPP_DMA4 and SSPP_DMA5 units to blend
stages. Add proper support for this register to allow using these two
planes for image processing.
Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550")
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550
Patchwork: https://patchwork.freedesktop.org/patch/518481/
Link: https://lore.kernel.org/r/20230116063316.728496-1-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index a35ecb6676c8..12c37faeeb09 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -17,6 +17,8 @@ (0x70 + (((lm) - LM_0) * 0x004)) #define CTL_LAYER_EXT3(lm) \ (0xA0 + (((lm) - LM_0) * 0x004)) +#define CTL_LAYER_EXT4(lm) \ + (0xB8 + (((lm) - LM_0) * 0x004)) #define CTL_TOP 0x014 #define CTL_FLUSH 0x018 #define CTL_START 0x01C @@ -383,6 +385,7 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx, struct dpu_hw_blk_reg_map *c = &ctx->hw; u32 mixercfg = 0, mixercfg_ext = 0, mix, ext; u32 mixercfg_ext2 = 0, mixercfg_ext3 = 0; + u32 mixercfg_ext4 = 0; int i, j; int stages; int pipes_per_stage; @@ -492,6 +495,20 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx, mixercfg_ext2 |= mix << 4; } break; + case SSPP_DMA4: + if (rect_index == DPU_SSPP_RECT_1) { + mixercfg_ext4 |= ((i + 1) & 0xF) << 8; + } else { + mixercfg_ext4 |= ((i + 1) & 0xF) << 0; + } + break; + case SSPP_DMA5: + if (rect_index == DPU_SSPP_RECT_1) { + mixercfg_ext4 |= ((i + 1) & 0xF) << 12; + } else { + mixercfg_ext4 |= ((i + 1) & 0xF) << 4; + } + break; case SSPP_CURSOR0: mixercfg_ext |= ((i + 1) & 0xF) << 20; break; @@ -509,6 +526,8 @@ exit: DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg_ext); DPU_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg_ext2); DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg_ext3); + if ((test_bit(DPU_CTL_HAS_LAYER_EXT4, &ctx->caps->features))) + DPU_REG_WRITE(c, CTL_LAYER_EXT4(lm), mixercfg_ext4); } |