diff options
| author | Thierry Reding <treding@nvidia.com> | 2019-12-09 13:00:04 +0100 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2020-01-15 10:49:59 +1000 |
| commit | 0d0d498265e7cb3329d2a7185b1d7cfb3be95d65 (patch) | |
| tree | 6c7b57f1c2c9e2424fe05157686d58c5917fb573 /drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h | |
| parent | 6992ceb8c0f6f8e2f4374a1ab4dd84cd76cc4b64 (diff) | |
drm/nouveau/ltc/gp10b: Add custom L2 cache implementation
There are extra registers that need to be programmed to make the level 2
cache work on GP10B, such as the stream ID register that is used when an
SMMU is used to translate memory addresses.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h')
| -rw-r--r-- | drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h index 644d527c3b96..d76f60d7d29a 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h @@ -40,4 +40,5 @@ int gm107_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); int gm200_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); int gp100_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); int gp102_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); +int gp10b_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); #endif |