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| author | James Morris <jmorris@namei.org> | 2010-05-06 10:56:07 +1000 |
|---|---|---|
| committer | James Morris <jmorris@namei.org> | 2010-05-06 10:56:07 +1000 |
| commit | 0ffbe2699cda6afbe08501098dff8a8c2fe6ae09 (patch) | |
| tree | 81b1a2305d16c873371b65c5a863c0268036cefe /drivers/gpu/drm/nouveau/nv40_graph.c | |
| parent | 4e5d6f7ec3833c0da9cf34fa5c53c6058c5908b6 (diff) | |
| parent | 7ebd467551ed6ae200d7835a84bbda0dcadaa511 (diff) | |
Merge branch 'master' into next
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv40_graph.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nv40_graph.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c index 53e8afe1dcd1..0616c96e4b67 100644 --- a/drivers/gpu/drm/nouveau/nv40_graph.c +++ b/drivers/gpu/drm/nouveau/nv40_graph.c @@ -335,6 +335,27 @@ nv40_graph_init(struct drm_device *dev) nv_wr32(dev, 0x400b38, 0x2ffff800); nv_wr32(dev, 0x400b3c, 0x00006000); + /* Tiling related stuff. */ + switch (dev_priv->chipset) { + case 0x44: + case 0x4a: + nv_wr32(dev, 0x400bc4, 0x1003d888); + nv_wr32(dev, 0x400bbc, 0xb7a7b500); + break; + case 0x46: + nv_wr32(dev, 0x400bc4, 0x0000e024); + nv_wr32(dev, 0x400bbc, 0xb7a7b520); + break; + case 0x4c: + case 0x4e: + case 0x67: + nv_wr32(dev, 0x400bc4, 0x1003d888); + nv_wr32(dev, 0x400bbc, 0xb7a7b540); + break; + default: + break; + } + /* Turn all the tiling regions off. */ for (i = 0; i < pfb->num_tiles; i++) nv40_graph_set_region_tiling(dev, i, 0, 0, 0); |