diff options
| author | Ben Skeggs <bskeggs@redhat.com> | 2012-07-22 11:55:54 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2012-10-03 13:12:55 +1000 |
| commit | f589be88caf32501a734e531180d5df5d6089ef3 (patch) | |
| tree | c6653b5d6aa47aade8abc79c0bb73462f82eef01 /drivers/gpu/drm/nouveau/nv84_fence.c | |
| parent | bc9e7b9a61e9e92ddb58920cb2cb5c2e2825ca8a (diff) | |
drm/nouveau/pageflip: kick flip handling out of engsw and into fence
This is all very much a policy thing, and hence will not belong in SW
after the rework.
engsw now only handles receiving the event to say "can flip now" and makes
a callback to perform the actual work.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv84_fence.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nv84_fence.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c index a1812cab19dc..5ef87edb878d 100644 --- a/drivers/gpu/drm/nouveau/nv84_fence.c +++ b/drivers/gpu/drm/nouveau/nv84_fence.c @@ -28,6 +28,7 @@ #include <engine/fifo.h> #include <core/ramht.h> #include "nouveau_fence.h" +#include "nv50_display.h" struct nv84_fence_chan { struct nouveau_fence_chan base; @@ -99,7 +100,7 @@ nv84_fence_context_new(struct nouveau_channel *chan) struct nv84_fence_priv *priv = dev_priv->fence.func; struct nv84_fence_chan *fctx; struct nouveau_gpuobj *obj; - int ret; + int ret, i; fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); if (!fctx) @@ -117,6 +118,23 @@ nv84_fence_context_new(struct nouveau_channel *chan) nv_wo32(priv->mem, chan->id * 16, 0x00000000); } + /* dma objects for display sync channel semaphore blocks */ + for (i = 0; i < chan->dev->mode_config.num_crtc; i++) { + struct nv50_display *pdisp = nv50_display(chan->dev); + struct nv50_display_crtc *dispc = &pdisp->crtc[i]; + struct nouveau_gpuobj *obj = NULL; + + ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, + dispc->sem.bo->bo.offset, 0x1000, + NV_MEM_ACCESS_RW, + NV_MEM_TARGET_VRAM, &obj); + if (ret) + break; + + ret = nouveau_ramht_insert(chan, NvEvoSema0 + i, obj); + nouveau_gpuobj_ref(NULL, &obj); + } + if (ret) nv84_fence_context_del(chan); return ret; |