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authorAlexandre Courbot <acourbot@nvidia.com>2017-02-23 18:41:41 +0900
committerBen Skeggs <bskeggs@redhat.com>2017-03-07 17:05:13 +1000
commitb62880f7966781eb0b3b1e50f63d6aac362476d3 (patch)
tree3db7e7808baadcfbe10d329a9bfd79bfcd4b008e /drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h
parent16307b5d720af3fec8d2153a68e23066e20c481f (diff)
drm/nouveau/core: add SEC2 engine
SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons unknown). Even though it shares the same address range as SEC, its usage is quite different and this justifies a new engine. Add this engine and make TOP use it all post-TOP devices should use this implementation and not the older SEC. Also quickly add the short gp102 implementation which will be used for falcon booting purposes. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h')
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h
new file mode 100644
index 000000000000..7ecc9d4724dc
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h
@@ -0,0 +1,9 @@
+#ifndef __NVKM_SEC2_PRIV_H__
+#define __NVKM_SEC2_PRIV_H__
+#include <engine/sec2.h>
+
+#define nvkm_sec2(p) container_of((p), struct nvkm_sec2, engine)
+
+int nvkm_sec2_new_(struct nvkm_device *, int, struct nvkm_sec2 **);
+
+#endif