diff options
| author | Peter Ujfalusi <peter.ujfalusi@ti.com> | 2016-09-22 14:06:48 +0300 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2016-11-02 10:48:18 +0200 |
| commit | 4dc2250d7d9e816b986d656cde90f55c096012ed (patch) | |
| tree | e6aab55339297cd000c19cc9f70ba45431ff8bf1 /drivers/gpu/drm/omapdrm/dss/hdmi_wp.c | |
| parent | fb7f3c4399ffa75bc31aaaaeab45238ea60c3d1a (diff) | |
drm/omap: omap_display_timings: rename hsw to hsync_len
In preparation to move the stack to use the generic videmode struct for
display timing information rename the hsw member to hsync_len.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/gpu/drm/omapdrm/dss/hdmi_wp.c')
| -rw-r--r-- | drivers/gpu/drm/omapdrm/dss/hdmi_wp.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c index 05462cfe5af8..89914a7a2bf9 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c @@ -166,24 +166,24 @@ void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, { u32 timing_h = 0; u32 timing_v = 0; - unsigned hsw_offset = 1; + unsigned hsync_len_offset = 1; DSSDBG("Enter hdmi_wp_video_config_timing\n"); /* * On OMAP4 and OMAP5 ES1 the HSW field is programmed as is. On OMAP5 - * ES2+ (including DRA7/AM5 SoCs) HSW field is programmed to hsw-1. + * ES2+ (including DRA7/AM5 SoCs) HSW field is programmed to hsync_len-1. * However, we don't support OMAP5 ES1 at all, so we can just check for * OMAP4 here. */ if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 || omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 || omapdss_get_version() == OMAPDSS_VER_OMAP4) - hsw_offset = 0; + hsync_len_offset = 0; timing_h |= FLD_VAL(timings->hbp, 31, 20); timing_h |= FLD_VAL(timings->hfp, 19, 8); - timing_h |= FLD_VAL(timings->hsw - hsw_offset, 7, 0); + timing_h |= FLD_VAL(timings->hsync_len - hsync_len_offset, 7, 0); hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h); timing_v |= FLD_VAL(timings->vbp, 31, 20); @@ -203,7 +203,7 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, timings->hbp = param->timings.hbp; timings->hfp = param->timings.hfp; - timings->hsw = param->timings.hsw; + timings->hsync_len = param->timings.hsync_len; timings->vbp = param->timings.vbp; timings->vfp = param->timings.vfp; timings->vsw = param->timings.vsw; @@ -223,7 +223,7 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, if (param->timings.double_pixel) { video_fmt->x_res *= 2; timings->hfp *= 2; - timings->hsw *= 2; + timings->hsync_len *= 2; timings->hbp *= 2; } } |