diff options
| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2023-11-09 11:25:41 +0100 |
|---|---|---|
| committer | Steven Price <steven.price@arm.com> | 2023-11-10 14:12:07 +0000 |
| commit | 32f175d4261a2c940fe7913f509f9f41c105b2b6 (patch) | |
| tree | ceadbacd5f42ca920fe0d0e0b128b7da0c2615a2 /drivers/gpu/drm/panfrost | |
| parent | 56e76c0179185568049913257c18069293f8bde9 (diff) | |
drm/panfrost: Set clocks on/off during system sleep on MediaTek SoCs
All of the MediaTek SoCs supported by Panfrost can switch the clocks
off and on during system sleep to save some power without any user
experience penalty.
Measurements taken on multiple MediaTek SoCs (MT8183/8186/8192/8195)
show that adding this will not prolong the time that is required to
resume the system in any meaningful way.
As an example, for MT8195 - a "before" with only runtime PM operations
(so, without turning on/off GPU clocks), and an "after" executing both
the system sleep .resume() handler and .runtime_resume() (so the time
refers to T_Resume + T_Runtime_Resume):
Average Panfrost-only system sleep resume time, before: ~28000ns
Average Panfrost-only system sleep resume time, after: ~33500ns
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Signed-off-by: Steven Price <steven.price@arm.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231109102543.42971-5-angelogioacchino.delregno@collabora.com
Diffstat (limited to 'drivers/gpu/drm/panfrost')
| -rw-r--r-- | drivers/gpu/drm/panfrost/panfrost_drv.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c index 54d1c19bea84..6d2897c03a8f 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -730,6 +730,7 @@ static const struct panfrost_compatible mediatek_mt8183_b_data = { .supply_names = mediatek_mt8183_b_supplies, .num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains), .pm_domain_names = mediatek_mt8183_pm_domains, + .pm_features = BIT(GPU_PM_CLK_DIS), }; static const char * const mediatek_mt8186_pm_domains[] = { "core0", "core1" }; @@ -738,6 +739,7 @@ static const struct panfrost_compatible mediatek_mt8186_data = { .supply_names = mediatek_mt8183_b_supplies, .num_pm_domains = ARRAY_SIZE(mediatek_mt8186_pm_domains), .pm_domain_names = mediatek_mt8186_pm_domains, + .pm_features = BIT(GPU_PM_CLK_DIS), }; static const char * const mediatek_mt8192_supplies[] = { "mali", NULL }; @@ -748,6 +750,7 @@ static const struct panfrost_compatible mediatek_mt8192_data = { .supply_names = mediatek_mt8192_supplies, .num_pm_domains = ARRAY_SIZE(mediatek_mt8192_pm_domains), .pm_domain_names = mediatek_mt8192_pm_domains, + .pm_features = BIT(GPU_PM_CLK_DIS), }; static const struct of_device_id dt_match[] = { |