diff options
| author | Marek Olšák <marek.olsak@amd.com> | 2017-02-13 17:37:05 +0100 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-03-29 23:53:03 -0400 |
| commit | 75cb00dc0c9dbe5e7a971ac729384d8d05f0deb1 (patch) | |
| tree | 97a5921be549f23b1070672e5551f11bf36f55bc /drivers/gpu/drm/radeon/cik.c | |
| parent | 451bc8eb8fe61ee89ebf44e7ee290ab88bb2b2d5 (diff) | |
drm/radeon: allow unaligned shader loads on CIK
Set alignment mode to unaligned on CIK to align with amdgpu. This is
needed for unaligned loads to work properly in mesa. The current setting
requires dword alignment.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/cik.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/cik.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index f6ff41a0eed6..ac0d93936d77 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -35,6 +35,9 @@ #include "clearstate_ci.h" #include "radeon_kfd.h" +#define SH_MEM_CONFIG_GFX_DEFAULT \ + ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED) + MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin"); MODULE_FIRMWARE("radeon/BONAIRE_me.bin"); MODULE_FIRMWARE("radeon/BONAIRE_ce.bin"); @@ -5587,7 +5590,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev) for (i = 0; i < 16; i++) { cik_srbm_select(rdev, 0, 0, 0, i); /* CP and shaders */ - WREG32(SH_MEM_CONFIG, 0); + WREG32(SH_MEM_CONFIG, SH_MEM_CONFIG_GFX_DEFAULT); WREG32(SH_MEM_APE1_BASE, 1); WREG32(SH_MEM_APE1_LIMIT, 0); WREG32(SH_MEM_BASES, 0); @@ -5794,7 +5797,7 @@ void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, radeon_ring_write(ring, 0); radeon_ring_write(ring, 0); /* SH_MEM_BASES */ - radeon_ring_write(ring, 0); /* SH_MEM_CONFIG */ + radeon_ring_write(ring, SH_MEM_CONFIG_GFX_DEFAULT); /* SH_MEM_CONFIG */ radeon_ring_write(ring, 1); /* SH_MEM_APE1_BASE */ radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */ |