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authorSlava Grigorev <slava.grigorev@amd.com>2014-12-09 16:44:18 -0500
committerAlex Deucher <alexander.deucher@amd.com>2015-01-22 10:42:14 -0500
commit1852c9a09a25aad40c80b0012ad19379b1fb78be (patch)
treef23f88376cea027ed0e0b392b238fe791587eec7 /drivers/gpu/drm/radeon/dce3_1_afmt.c
parentbaa7d8e451f030c049f83f943b9995620d6d6bd3 (diff)
radeon/audio: moved audio packet programming to a separate function
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Slava Grigorev <slava.grigorev@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/dce3_1_afmt.c')
-rw-r--r--drivers/gpu/drm/radeon/dce3_1_afmt.c56
1 files changed, 26 insertions, 30 deletions
diff --git a/drivers/gpu/drm/radeon/dce3_1_afmt.c b/drivers/gpu/drm/radeon/dce3_1_afmt.c
index 3ec9dea76ed1..cf788db5873a 100644
--- a/drivers/gpu/drm/radeon/dce3_1_afmt.c
+++ b/drivers/gpu/drm/radeon/dce3_1_afmt.c
@@ -199,6 +199,27 @@ void dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset,
~HDMI0_ACR_N_48_MASK);
}
+void dce3_2_set_audio_packet(struct drm_encoder *encoder, u32 offset)
+{
+ struct drm_device *dev = encoder->dev;
+ struct radeon_device *rdev = dev->dev_private;
+
+ WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
+ HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
+ HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
+
+ WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
+ AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
+ AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
+
+ WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
+ HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
+ HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
+
+ WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,
+ HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
+}
+
/*
* update the info frames with the data from the current display mode
*/
@@ -226,41 +247,16 @@ void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *m
radeon_audio_set_vbi_packet(encoder);
radeon_hdmi_set_color_depth(encoder);
- if (ASIC_IS_DCE32(rdev)) {
- WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
- HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
- HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
- WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
- AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
- AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
- } else {
- WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
- HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
- HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
- HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
- HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
- }
-
- if (ASIC_IS_DCE32(rdev)) {
- radeon_audio_write_speaker_allocation(encoder);
- radeon_audio_write_sad_regs(encoder);
- }
-
- /* TODO: HDMI0_AUDIO_INFO_UPDATE */
- WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
- HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
- HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
-
- WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,
- HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
-
WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */
+ radeon_audio_update_acr(encoder, mode->clock);
+ radeon_audio_write_speaker_allocation(encoder);
+ radeon_audio_set_audio_packet(encoder);
+ radeon_audio_write_sad_regs(encoder);
+
if (radeon_audio_set_avi_packet(encoder, mode) < 0)
return;
- radeon_audio_update_acr(encoder, mode->clock);
-
/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);